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74AC541 * 74ACT541 Octal Buffer/Line Driver with 3-STATE Outputs
November 1988 Revised March 2005
74AC541 * 74ACT541 Octal Buffer/Line Driver with 3-STATE Outputs
General Description
The 74AC541 and 74ACT541 are octal buffer/line drivers designed to be employed as memory and address drivers, clock drivers and bus oriented transmitter/receivers. These devices are similar in function to the 74AC244 and 74ACTC244 while providing flow-through architecture (inputs on opposite side from outputs). This pinout arrangement makes these devices especially useful as an output port for microprocessors, allowing ease of layout and greater PC board density.
Features
s ICC and IOZ reduced by 50% s 3-STATE outputs s Inputs and outputs opposite side of package, allowing easier interface to microprocessors s Output source/sink 24 mA s 74AC541 is a non-inverting option of the 74AC540 s 74ACT541 has TTL-compatible inputs
Ordering Code:
Order Number 74AC541SC 74AC541SJ 74AC541MTC 74AC541MTCX_NL (Note 1) 74AC541PC 74ACT541SC 74ACT541MTC 74ACT541MTCX_NL (Note 1) 74ACT541PC Package Number M20B M20D MTC20 MTC20 N20A M20B MTC20 MTC20 N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code. Pb-Free package per JEDED J-STD-020B. Note 1: "_NL" indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
FACT is a trademark of Fairchild Semiconductor Corporation.
(c) 2005 Fairchild Semiconductor Corporation
DS009967
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74AC541 * 74ACT541
Logic Symbol
IEEE/IEC
Connection Diagram
Truth Table
Inputs OE1 L H X L
H HIGH Voltage Level X Immaterial L
Outputs I H X X L H Z Z L
Z High Impedance
OE2 L X H L
LOW Voltage Level
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2
74AC541 * 74ACT541
Absolute Maximum Ratings(Note 2)
Supply Voltage (VCC) DC Input Diode Current (IIK) VI VI
0.5V to 7.0V 20 mA 20 mA 0.5V to VCC 0.5V 20 mA 20 mA 0.5V to VCC 0.5V r 50 mA r 50 mA 65qC to 150qC
140qC
Recommended Operating Conditions
Supply Voltage (VCC) AC ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate ('V/'t) AC: VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V ACT:VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V
Note 2: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications.
0.5V VCC 0.5V
2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC
DC Input Voltage (VI) DC Output Diode Current (IOK) VO VO
0.5V
VCC 0.5V
40qC to 85qC
125 mV/ns
DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) PDIP
DC Electrical Characteristics for AC
Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VCC (V) 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 VOL Maximum LOW Level Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 IIN (Note 5) IOZ Maximum Input Leakage Current Maximum 3-STATE Leakage Current IOLD IOHD Minimum Dynamic Output Current (Note 4) 5.5 5.5 5.5 5.5 4.0 5.5 0.002 0.001 0.001 TA Typ 1.5 2.25 2.75 1.5 2.25 2.75 2.99 4.49 5.49 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.56 3.86 4.86 0.1 0.1 0.1 0.36 0.36 0.36
25qC
TA
40qC to 85qC
2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4
Units VOUT V
Conditions 0.1V
Guaranteed Limits or VCC 0.1V VOUT V 0.1V
or VCC 0.1V
V
IOUT VIN
50 PA
VIL or VIH
2.46 3.76 4.76 0.1 0.1 0.1
V
IOH IOH IOH
12 mA 24 mA 24 mA (Note 3)
50 PA VIL or VIH 12 mA 24 mA 24 mA (Note 3) V CC, GND V IL, VIH VCC, GND VCC, GND 1.65V Max 3.85V Min VCC or GND
V
IOUT VIN
0.44 0.44 0.44
V
IOL IOL IOL VI VI VO
r 0.1 r0.25
r 1.0 r2.5
75
PA PA
mA mA
VI (OE)
VOLD VOHD VIN
75
40.0
ICC (Note 5) Maximum Quiescent Supply Current
PA
Note 3: All outputs loaded; thresholds on input associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time. Note 5: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
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74AC541 * 74ACT541
AC Electrical Characteristics for AC
VCC Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Propagation Delay Data to Output Propagation Delay Data to Output Output Enable Time Output Enable Time Output Disable Time Output Disable Time (V) (Note 6) 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0
Note 6: Voltage Range 3.3 is 3.3V r 0.3V Voltage Range 5.0 is 5.0V r 0.5V
TA CL Min 2.0 1.5 2.0 1.5 3.0 2.0 2.5 1.5 3.5 2.0 2.5 2.0
25qC
50 pF Typ 5.5 4.0 5.5 4.0 8.0 6.0 7.0 5.5 9.0 7.0 6.5 5.5 Max 8.0 6.0 8.0 6.0 11.5 8.5 10.0 7.5 12.5 9.5 9.5 7.5
TA
40qC to 85qC
CL 50 pF Max 9.0 6.5 8.5 6.5 12.5 9.5 11.5 8.5 14.0 10.5 10.5 8.5 ns ns ns ns ns ns Units
Min 1.5 1.0 1.5 1.0 3.0 1.5 2.5 1.0 2.5 1.0 2.0 1.0
DC Electrical Characteristics for ACT
Symbol VIH VIL VOH Parameter Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage VCC (V) 4.5 5.5 4.5 5.5 3.0 4.5 4.5 5.5 VOL Maximum LOW Level Output Voltage 3.0 4.5 4.5 5.5 IIN IOZ ICCT IOLD IOHD ICC Maximum Input Leakage Current Maximum 3-STATE Leakage Current Maximum ICC/Input Minimum Dynamic Output Current (Note 8) Maximum Quiescent Supply Current
Note 7: All outputs loaded; thresholds on input associated with output under test. Note 8: Maximum test duration 2.0 ms, one output loaded at a time.
TA Typ 1.5 1.5 1.5 1.5 2.99 4.49
25qC
2.0 2.0 0.8 0.8 2.9 4.4 3.86 4.86
TA
40qC to 85qC
2.0 2.0 0.8 0.8 2.9 4.4 3.76 4.76 0.1 0.1 0.44 0.44
Guaranteed Limits
Units V V V VOUT VOUT IOUT VIN V IOH IOH IOUT VIN V IOH IOH VI VI VO VI VOLD VOHD VIN
Conditions 0.1V 0.1V
or VCC 0.1V or VCC 0.1V
50 PA
VIL or VIH
24 mA 24 mA (Note 7)
50 PA VIL or VIH 24 mA 24 mA (Note 7) V CC, GND V IL, VIH VCC, GND VCC 2.1V 1.65V Max 3.85V Min VCC or GND
0.002 0.001
0.1 0.1 0.36 0.36
V
5.5 5.5 5.5 5.5 5.5 5.5 0.6
r 0.1 r0.25
r 1.0 r2.5
1.5 75
PA
PA
mA mA mA
75
4.0 40.0
PA
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74AC541 * 74ACT541
AC Electrical Characteristics for ACT
V CC Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ
Note 9: Voltage Range 5.0 is 5.0V r 0.5V
TA CL Min 2.0 2.0 2.0 2.0 1.5 1.5
25qC
50 pF Typ 4.5 5.5 5.0 6.5 5.5 5.5 Max 7.0 7.0 9.0 9.0 7.5 7.5
TA
40qC to 85qC
CL 50 pF Max 7.5 7.5 9.5 9.5 8.0 8.0 ns ns ns Units
Parameter Propagation Delay Data to Output Output Enable Time Output Disable Time
(V) (Note 9) 5.0 5.0 5.0
Min 2.0 2.0 2.0 2.0 1.5 1.5
Capacitance
Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance for AC Power Dissipation Capacitance for ACT Typ 4.5 30.0 70.0 Units pF pF VCC VCC OPEN 5.0V Conditions
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74AC541 * 74ACT541
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B
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74AC541 * 74ACT541
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D
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74AC541 * 74ACT541
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20
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74AC541 * 74ACT541 Octal Buffer/Line Driver with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 9 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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